1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a circuit for driving a non-volatile ferroelectric memory.
2. Background of the Related Art
A ferroelectric random access memory (FRAM) has a data processing speed as fast as a DRAM and conserves data even after the power is turned off. The FRAM includes capacitors similar to the DRAM, but the capacitors have a ferroelectric substance for utilizing the characteristic of a high residual polarization of the ferroelectric substance in which data is not lost even after eliminating an electric field applied thereto.
FIG. 1 illustrates a general hysteresis loop of a ferroelectric substance. As shown in the hysteresis loop in FIG. 1, a polarization induced by an electric field does not vanish, but remains at a certain portion (xe2x80x9cdxe2x80x9d or xe2x80x9caxe2x80x9d state) even after the electric field is cleared due to an existence of a spontaneous polarization. These xe2x80x9cdxe2x80x9d and xe2x80x9caxe2x80x9d states may be matched to binary values of xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d for use as a memory cell. The state in which a positive voltage is applied to a ferroelectric memory cell is a xe2x80x9ccxe2x80x9d state in FIG. 1, the state in which no voltage is applied thereafter is a xe2x80x9cdxe2x80x9d state. Opposite to this, if a negative voltage is applied to the ferroelectric memory cell, the state moves from the xe2x80x9cdxe2x80x9d to an xe2x80x9cfxe2x80x9d state, and the state in which no voltage is applied thereafter is an xe2x80x9caxe2x80x9d state. If a positive voltage is applied again, the states moves to the xe2x80x9ccxe2x80x9d state via the xe2x80x9cbxe2x80x9d state. Thus, a data can be stored in stable states of xe2x80x9caxe2x80x9d and xe2x80x9cdxe2x80x9d. On the hysteresis loop, xe2x80x9ccxe2x80x9d and xe2x80x9cdxe2x80x9d states correspond to a binary logic value of xe2x80x9c1xe2x80x9d, and xe2x80x9caxe2x80x9d and xe2x80x9cfxe2x80x9d states correspond to a binary logic value xe2x80x9c0xe2x80x9d.
FIG. 2 illustrates a unit cell of a background art ferroelectric memory. The unit cell of a background art ferroelectric memory is provided with a bitline B/L formed in a direction, a wordline W/L formed in a direction crossing the bitline, a plateline P/L formed in the same direction with the wordline spaced therefrom, a transistor T1 having a gate connected to the wordline and a source connected to the bitline, and a ferroelectric capacitor FC1 having a first terminal connected to a drain of the transistor T1 and a second terminal connected to the plateline.
FIGS. 3a and 3b together illustrate a circuit for driving the background art one transistor/one capacitor (1T/1C) ferroelectric memory of FIG. 2. A reference voltage generator generates a reference voltage, and a reference voltage stabilizer 2 having a plurality of transistors Q1xcx9cQ4 and a capacitor C1 stabilizes a reference voltage on two adjacent bitlines B1 and B2 because the reference voltage from the reference voltage generator 1 can not be provided to a sense amplifier directly. A first reference voltage storage part 3 having a plurality of transistors Q6xcx9cQ7 and capacitors C2xcx9cC3 stores logic value xe2x80x9c1xe2x80x9d and a logic value xe2x80x9c0xe2x80x9d in adjacent bit lines. A first equalizer 4 having a transistor Q5 equalizes adjacent two bitlines.
A first main cell array 5 connected to wordlines W/L and platelines P/L different from one another stores data, and a first sense amplifier 6 having a plurality of transistors Q10xcx9cQ15 and P-sense amplifiers PSA senses a data in a cell selected by the wordline from the plurality of cells in the main cell array part 5. A second main cell array 7 connected to wordlines and platelines different from one another stores data, and a second reference voltage storage 8 having a plurality of transistors Q28xcx9cQ29 and capacitors C9xcx9cC10 stores a logic value xe2x80x9c1xe2x80x9d and a logic value xe2x80x9c0xe2x80x9d in adjacent bit lines. A second sense amplifier 9 having a plurality of transistors Q16xcx9cQ25 and N-sense amplifiers NSA senses a data in the second main cell array 7.
FIG. 4 illustrates a timing diagram showing a write mode operation of the background art ferroelectric memory. First, when a chip enable signal CSBpad received externally is enabled from xe2x80x9chighxe2x80x9d to xe2x80x9clowxe2x80x9d and a write enable signal WEBpad also transits from xe2x80x9chighxe2x80x9d to xe2x80x9clowxe2x80x9d, the write mode is started. An address decoding is started in the write mode, to transit a pulse applied to a selected wordline from xe2x80x9clowxe2x80x9d to xe2x80x9chighxe2x80x9d to a selected cell. In an interval where the wordline is thus held at xe2x80x9chighxe2x80x9d, a corresponding plateline P/L is applied of a xe2x80x9chighxe2x80x9d signal for an interval and a xe2x80x9clowxe2x80x9d signal for an interval in a sequence and a corresponding bitline is applied of a xe2x80x9chighxe2x80x9d or xe2x80x9clowxe2x80x9d signal synchronous to the write enable signal, for writing a logic xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d on the selected cell. In other words, if a signal applied to the plateline is xe2x80x9clowxe2x80x9d in an interval where the bitline is applied of a xe2x80x9chighxe2x80x9d signal and the wordline is applied of a xe2x80x9chighxe2x80x9d signal, a logic value xe2x80x9c1xe2x80x9dis written in the ferroelectric capacitor. If a signal applied to the plateline is xe2x80x9chighxe2x80x9d and the bitline is applied of a xe2x80x9clowxe2x80x9d signal, a logic value xe2x80x9c0xe2x80x9d is written in the ferroelectric capacitor.
The operation for reading a data stored in a cell with the write mode operation will be explained with reference to FIG. 5. When the chip enable signal CSBpad is enabled from xe2x80x9chighxe2x80x9d to xe2x80x9clowxe2x80x9d externally, all bitlines are equalized to xe2x80x9clowxe2x80x9d by an equalizer signal before selection of a corresponding wordline. As shown in FIGS. 3a and 3b, when a xe2x80x9chighxe2x80x9d signal is applied to the equalizer 4 and a xe2x80x9chighxe2x80x9d signal is applied to transistors Q18 and Q19 grounding the bitlines through transistors Q18 and Q19, the bitlines are equalized to a low voltage Vss. The transistors Q5, Q18 and Q19 are turned off, disabling corresponding bitlines, and address is decoded for transiting a corresponding wordline from xe2x80x9clowxe2x80x9d to xe2x80x9chighxe2x80x9d, to select a corresponding cell. Then, a xe2x80x9chighxe2x80x9d signal is applied to a plateline of the selected cell, to cancel data corresponding to a logic value xe2x80x9c1xe2x80x9d stored in a FRAM. If the FRAM is in storage of a logic value xe2x80x9c0xe2x80x9d, a data corresponding to it will not be canceled. A cell with a canceled data and a cell with a data not canceled provide signals different from each other according to the aforementioned hysteresis loop principle. Data provided through the bitline is sensed by the sense amplifier of a logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d.
That is, referring to FIG. 1, since the case of a canceled data is a case when a state is changed from xe2x80x9cdxe2x80x9d to xe2x80x9cfxe2x80x9d, and the case of a data not canceled is a case when a state is changed from xe2x80x9caxe2x80x9d to xe2x80x9cfxe2x80x9d, if the sense amplifier is enabled after a certain time, in the case of the canceled data, the data is amplified to provide a logic value xe2x80x9c1xe2x80x9d, and, in the case of the data not canceled, the data is amplified to provide a logic value xe2x80x9c0xe2x80x9d. After the sense amplifier amplifies and provides a signal, since the cell should be recovered of an original data, during xe2x80x9chighxe2x80x9d is applied to a corresponding line, the plateline is disabled from xe2x80x9chighxe2x80x9d to xe2x80x9clowxe2x80x9d. However, in the background art 1T/1C ferroelectric memory, in which the reference cell is operative more than the main memory cell in data input and output operations, the reference cell degrades rapidly.
Accordingly, the background art ferroelectric memory and a circuit for driving the same have various disadvantages. Since one reference cell of a ferroelectric substance of which ferroelectric property is not fully assured is provided for several hundreds cells of main memories for use in reading operation, requiring much more operation of the reference cell, the reference cell experience a rapid degradation of the ferroelectric property, causing instability of the reference voltage and subsequent degradation of device operation performance and life time.
Accordingly, the present invention is directed a circuit for driving a nonvolatile ferroelectric memory that substantially obviates one or more of the problems due to limitations and disadvantages of the related art and to provide at least the advantages described hereinafter.
An object of the present invention is to provide a circuit for driving a nonvolatile ferroelectric memory which improves device operation performance and life time.
Another object of the present invention is to provide a circuit for driving a non-volatile ferroelectric memory, in which a driver has an NMOS boost circuit for simplifying a system of wordline driver and applying a boosted voltage to a wordline without loss of a threshold voltage, whereby improving a current driving capability and effective use of a layout area.
To achieve these and other advantages in a whole or in parts and in accordance with the purpose of the present invention, as embodied and broadly described, a circuit for driving a memory, the memory including a memory array having a plurality of memory cells, pairs of first and second wordlines extending along a first direction spaced from each other, each pair of first and second wordlines corresponding to one of a plurality of global wordlines extending in the first direction, and a plurality of bitlines extending in a second direction crossing the wordline pairs, each memory cell coupled to a corresponding pair of first and second wordlines and a corresponding bitline, a first address circuit coupled to a global wordline to output first control signals, and a wordline driving signal circuit coupled to the first address circuit and the corresponding pair of first and second wordlines that receives the first control signals to enable the corresponding the first and second wordline.
To further achieve at least the above objects in a whole or in parts according to the present invention, there is provided a semiconductor memory device, including a memory array having pairs of first and second wordlines extending along a first direction spaced from each other, each pair corresponding to one of a plurality of global wordlines extending in the first direction, a plurality of bitlines extending in a second direction crossing the wordline pairs, a plurality of cell arrays having cells respectively coupled to a corresponding pair of first and second wordlines and a corresponding bitline, and a split wordline driver that selectively provides a driving signal to at least two of the cell arrays, and a driving circuit that includes a first address signal forwarder that includes a plurality of first transistors coupled to a global wordline in series, and a plurality of wordline pair driving signal forwarders coupled in parallel between the first address signal forwarder and corresponding pairs of first and second wordlines respectively coupled to first and second cell arrays to drive the corresponding pairs of first and second wordlines.
To further achieve at least the above objects in a whole or in parts according to the present invention, there is provided a circuit for driving a memory, the memory including a cell array of multi-NAND memory cells each with a plurality of transistors coupled in series to a bitline, wherein each of the transistors has a control electrode coupled to one of a plurality of wordlines, the circuit including an address signal circuit coupled to a global wordline to output first control signals, wherein the address signal circuit is controlled by a global decoder, and a wordline driving circuit that selectively applies a plurality of second control signals to the wordlines in sequence according to the first control signals.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.